Strain engineering approach improves performance of 2D semiconductor-based transistors

Manipulating mechanical strain in materials, also known as strain engineering, has enabled engineers to advance electronics over the past few decades, increasing the mobility of charge carriers within devices, for example. Over the past few years, several studies have been conducted to devise effective strategies for manipulating strain in two-dimensional (2D) semiconductors that are compatible with existing industrial processes.

Researchers at Stanford University recently introduced a CMOS-compatible approach for designing tensile strain (or stretchability) in single-layer semiconductor transistors.

The approach, outlined in a paper published in Nature Electronics, relies on the use of a silicon nitride capping layer that can strain single-layer molybdenum disulfide (MoS2) transistors integrated on a silicon substrate. I’m doing it.

“We started brainstorming this idea back in 2020, when our research group was working on initial efforts to strain samples by mechanically bending them,” the paper says. Senior author Eric Popp told Tech Xplore.

“At the time, there was little experimental demonstration of using strain to improve the performance of two-dimensional (2D) material transistors, and none had achieved this in an industry-friendly manner.

The main goal of recent research by Pop and his colleagues was to try to identify new and promising strain engineering techniques rooted in traditional silicon transistor processing that can be applied to 2D materials. After describing one of these techniques, they successfully applied it to a 2D MoS2-based transistor for the first time.

“Our strategy, inspired by the silicon industry of the early 2000s, uses a thin silicon nitride cap layer (a material widely used in the industry) to apply strain to 2D semiconductor transistors,” says Pop. he explained. “The stress in these films can be precisely tuned and they can be deposited at relatively low temperatures, making them advantageous for a variety of industrial applications.”

First, the researchers used established manufacturing techniques to fabricate a 2D semiconductor and use it to create a transistor. They added a silicon nitride film at the end of the process. This allowed us to clearly identify the influence of these films on transistor distortion and distinguish it from effects related to temperature changes and doping.

“The first notable contribution of this study is that process-induced strain (i.e., strain caused by various manufacturing steps during transistor fabrication) is present in these 2D material transistors and that techniques can be used to reduce the on-state current. “We have experimentally demonstrated that it can be used to increase the number of nanotubes that were previously used in silicon transistors,” Popp said.

“Importantly, we have also provided a simulation-based roadmap for how this strain will change as these devices are scaled down to technically appropriate dimensions. I realized that I have a hidden sexuality.”

In initial tests, researchers have found that a strain engineering approach can improve the performance of 2D MoS2 transistors while reducing both the transistor’s channel and contacts. In the future, their research could contribute to the development of smaller, better-performing 2D semiconductor-based transistors.

Meanwhile, Popp and his colleagues plan to continue testing and refining their proposed strain engineering technique. They also plan to investigate the effects of strain on other 2D semiconductors other than MoS2 monolayers.

“At a fundamental level, we are using flexible substrates to study the effects of strain in other, less understood 2D semiconductors,” Popp added.

“Additionally, we are investigating other sources of process-induced distortion, such as the effect of metal deposition on 2D materials (a critical step during device fabrication).Finally, we are investigating this approach (in contrast to ) are working on expanding to p-type 2D transistors, as their performance currently lags behind n-type devices. ”

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